1. Field of the Invention
The present invention relates generally to integrated circuit manufacture; and more particularly to an integrated circuit that includes a plurality of devices having insulative punchthrough regions
2. Description of the Related Art
The structure and the various components, or features, of a metal oxide semiconductor (MOS) device are generally well known. A MOS transistor typically includes a substrate material onto which a gate insulator and a patterned gate conductor are formed. The gate conductor serves to self-align impurities forwarded into the substrate on opposite sides of the gate conductor. The impurities placed into the substrate define a junction region, also known as source/drain regions. The gate conductor is patterned from a layer of polysilicon using various lithography techniques.
A typical n-channel MOS transistor employs n-type junctions placed into a p-type substrate. Conversely, a typical p-channel MOS transistor comprises p-type junctions placed into an n-type substrate. The substrate comprises an entire monolithic silicon wafer, of which, a portion of the substrate known as a "well" exists. The well is doped opposite the substrate so that it can accommodate junctions of an impurity type opposite the junction in the non-well areas. Accordingly, wells are often employed when both n-type and p-type transistors (i.e. Complementary MOS, "CMOS") are needed.
A pervasive trend in modern integrated circuit manufacture is to produce transistors having feature sizes as small as possible. To achieve a high density integrated circuit, features such as the gate conductor, source/drain junctions, and interconnects to the junction must be made as small as possible. Many modern day processes employ features which have less than 0.15 micron critical dimensions. As feature size decreases, the resulting transistor as well as the interconnect between transistors also decreases. Smaller transistors allow more transistors to be placed on a single monolithic substrate, thereby allowing relatively large circuit systems to be incorporated on a single and relatively small die area. Further, smaller transistors typically have lower turn-on threshold voltages, faster switching speeds and consume less power in their operation. These features in combination allow for higher speed integrated circuits to be constructed that have greater processing capabilities.
The benefits of high density circuits can only be realized if advanced processing techniques are used. For example, semiconductor process engineers and researchers often study the benefits of electron beam lithography and x-ray lithography to achieve the higher resolutions needed for submicron features. To some extent, wet etch has given way to a more advanced anisotropic (dry etch) technique. Further, silicides and polycides have replaced higher resistivity contact structures mostly due to the lower resistivity needed when a smaller contact area is encountered.
Many other techniques are often used to achieve a higher density circuit. However, these techniques must contend with problems resulting from higher density itself. Even the most advanced processing techniques cannot in all instances offset the problems associated with small features or features arranged extremely close to one another. For example, as the channel length decreases, short channel effects ("SCE") generally occur. SCE cause threshold voltage skews at the channel edges as well as excessive subthreshold currents (e.g., punch through and drain-induced barrier lowering). Related to SCE is the problem of hot carrier injection ("HCI"). As the channel shortens and the supply voltage remains constant, the electric field across the drain-to-channel junction becomes excessive. Excessive electric fields give rise to so called hot carriers and the injection of these carriers into the gate oxide which resides between the substrate (or well) and the overlying gate conductor. Injection of hot carriers should be avoided since these carriers can become trapped and skew the turn-on threshold voltage of the ensuing transistor.
In attempt to provide a design turn-on threshold voltage, the doping of channel regions of the transistors are enhanced at a surface region (V.sub.T region) of the channel. Further, to isolate the channel regions of the transistors from the substrate (or well), a punchthrough region is formed between the channel region and the substrate (or well). The punchthrough region aids in inverting the channel during turn-on by preventing leakage into the substrate. In forming the punchthrough region, a portion of the substrate (or well) adjacent the channel region is doped. For example, in an n-type transistor, the punchthrough region would be doped p-type using a Boron implant technique, for example. Likewise, in a p-type transistor, the punchthrough region is doped n-type using a Phosphorous implant technique, for example.
With a decrease in the dimensions of the transistor, however, the depth of the channel region is also decreased. With the decrease in depth of the channel region, the punchthrough region resides relatively closer to the V.sub.T region of the transistor. Since these regions are typically oppositely doped, migration of charges between the V.sub.T region and the punchthrough region becomes likely, causing the turn-on threshold voltage to be undesirably altered. Further, the doped punchthrough region causes the channel to be pinched, lowering the available source to drain current (I.sub.DS) provided by the transistor. The lowering of the I.sub.DS may prevent the integrated circuit within which the transistor is formed from operating as designed, at worst, and may cause the integrated circuit to be operable at a relatively lower speed.
Thus, there exists a need in the art for an improved transistor construction that overcomes the shortcomings caused by conventional punchthrough formation.